Future-Proof Security Solutions
for Low-Resource Devices

 

Ideally suited for the billions of devices (e.g., microcontrollers, ASICs, FPGAs, and sensors) headed for the IoT, our quantum-resistant cryptographic constructions are smaller, faster, and more energy-efficient than today’s commercially available platforms.

Walnut Digital Signature AlgorithmTM

Provides integrity, authentication, and non-repudiation between parties such as IoT devices and other endpoints

  • Key features and deliverables:
    • Synthesizable RTL — In Verilog and VHDL
    • Simulation and synthesis scripts — Automation for easy evaluation and implementation
    • Test vectors — Facilitates rapid testing
    • Verification and regression suites — Full test coverage to ensure design integrity
    • Executable C models — Verifies correct output from IP core
    • Cryptographic keys — To exercise both the hardware core and the C models
    • Interfaces — For Cortex-M0, 8051, and core processor blocks on FPGAs
  • Documentation — WalnutDSATM Overview (Download PDF)

Preparing for a post-quantum world: Concerns over the security threats of quantum computing having been growing such that the National Institute of Standards and Technology (NIST) has initiated a process to solicit, evaluate and standardize quantum-resistant, public key, cryptographic methods. In response to NIST’s call for solutions, SecureRF has submitted WalnutDSA, which is resistant to known quantum attacks. More details about the NIST project and WalnutDSA as a potential solution can be found here.

Ironwood Key Agreement ProtocolTM

Future-proof, Diffie-Hellman-like authentication protocol that is optimized for cost and power

  • Key features and deliverables:
    • Synthesizable RTL — In Verilog
    • Simulation and synthesis scripts — Automation for easy evaluation and implementation
    • Test vectors — Facilitates rapid testing
    • Verification and regression suites — Full test coverage to ensure design integrity
    • Executable C models — Verifies correct output from IP core
    • Cryptographic keys — To exercise both the hardware core and the C models
    • Interfaces — For Cortex-M0, 8051, and core processor blocks on FPGAs
    • Documentation and design support — For smooth implementation
    • Gate count as implemented in a 65-nm CMOS process: 20,000 typical gate utilization
    • Cycle count to compute shared secret at 128-bit security level: < 10,000 cycles
    • FPGA resource utilization, Xilinx xc7z010 — Slice LUTs: 7,122; Slice Registers: 2,324
  • Documentation — Ironwood KAPTM Overview (Download PDF)

Hickory Hash FunctionTM

Quantum-resistant cryptographic hash function ideal for constrained implementations

  • Many-to-one function, but it is computationally infeasible to find two inputs that result in the same output
  • Reuse the underlying engine to save silicon or code space